The FSBL does the following:Ĭonfigures the FPGA with the hardware bitstream (if it exists) On-chip ROM code is responsible for loading the first stage boot The processing system (PS) and it executes on-chip ROM code. The boot process is initiated by one of the Arm® Cortex™-A9 CPUs in Refer to the Zynq-7000 SoC Technical Reference Manual In this method, the master boot method is further divided into secure and non-secure Such as QSPI, NAND, NOR flash, and SD cards are used to store boot Images from non-volatile memory into the processor system (PS). In the master boot method, the CPU loads and executes the external boot Vitis Embedded Software Debugging Guide (UG1515) 2021.1.Example Setup for a Graphics and DisplayPort Based Sub-System.Profiling Applications with System Debugger.Creating Custom IP and Device Drivers for Linux.(Optional) Programning QSPI Flash with the Boot Image Using JTAG.Programming QSPI Flash with the Flash Programming Tool.Making a Linux Bootable Image for QSPI Flash with the Vitis IDE.Making a Linux Bootable Image for QSPI Flash with PetaLinux.Changing boot.scr for image.ub Offset Address and Size.Example 10: Booting Linux from QSPI Flash.Using the HP Slave Port with AXI CDMA IP.Building and Debugging Linux Applications for Zynq-7000 SoCs.

Debugging Standalone Applications with the Vitis Software Platform.Zynq UltraScale+ MPSoC Embedded Design Tutorial.